ESD impact on production yield and product quality is increasingly becoming more significant due to requirements for higher speeds and device scaling. In general, ESD protection devices work by providing a path through the integrated circuit (IC) that has high current shunting capabilities. Known PNP-based ESD protection solutions are not always latch-up safe, for example, they may rely on a typical n-type lateral double diffused metal-oxide-semiconductor ESD field effect transistor (LDNMOS ESDFET) that shows snapback (low holding voltage (VH)) outside of an ESD design window. In addition known PNP-based ESD protection solutions often require considerable device area, which can be an inefficient use of limited device area.
A need therefore exists for methodology enabling improved VH using a known or smaller ESD cell area and the resulting device.